Is it possible to connect PSIM (power electronics software) with OPAL-RT target?
Yes, it is possible to connect and integrate PSIM with an OPAL-RT real-time target.
There are several standard integration workflows depending on whether you want to run power electronics circuits on the FPGA (eHS), execute control algorithms on the CPU, or perform Controller Hardware-in-the-Loop (cHIL) testing.
- FPGA Real-Time Simulation via eHS (Circuit Netlist / Schematic Import)
OPAL-RT’s eHS (FPGA-based Electrical Hardware Solver, available in RT-LAB and HYPERSIM) natively supports power electronics topologies designed in third-party schematic tools, including PSIM:
How it works: You design your power stage (converters, inverters, passive filters, switches) in PSIM and import the netlist / schematic into OPAL-RT’s Schematic Editor / eHS workflow.
Target Execution: The circuit runs on the OPAL-RT target’s onboard FPGA at sub-microsecond time steps (e.g., 100\text{ ns} - 1,\mu\text{s}), enabling high-frequency PWM switching simulation without writing any VHDL/Verilog code.
- C-Code Generation via PSIM SimCoder (CPU Execution)
If you design digital control algorithms (e.g., FOC, MPPT, PLL, PWM modulators) in PSIM:
How it works: Use PSIM SimCoder (or C-block code export) to automatically generate ANSI C code from your PSIM control schematic.
Target Execution: Wrap the generated C code into a C-MEX S-Function or Simulink block within an RT-LAB model (or C-function in HYPERSIM). The control code compiles and runs in real time on the OPAL-RT target CPU cores.
- FMI / FMU (Functional Mock-up Interface) Co-Simulation
How it works: Export components or control blocks from PSIM as a Functional Mock-up Unit (FMU) supporting FMI 2.0.
Target Execution: Import the FMU into RT-LAB or HYPERSIM to execute co-simulation alongside power system models.
- Controller Hardware-in-the-Loop (cHIL) Setup
In standard power electronics testing workflows:
Controller side: PSIM + SimCoder generates embedded C code directly onto a physical microcontroller or DSP (such as a TI C2000 DSP board).
Plant side: The OPAL-RT target runs the real-time plant simulation (inverter, grid, DC sources, motors) on its CPU/FPGA.
Connection: Physical I/O signals (analog outputs for voltage/current sensing, digital inputs for high-speed PWM gate pulses) connect the DSP to the OPAL-RT simulator in closed loop.
@Parija Thank you for your help. I have eHs function in my target.
And I opened PSIM file as shown below. Do you know how to do next step if I want to import this into OPAL RT (eHs)?
Hi Vincent,
Great to see your interleaved PFC circuit!
Looking at your schematic, you currently have two parts: the power stage (AC source, diode bridge, L_1, L_2, Q_1, Q_2, D_1, D_2, output capacitor C_o, load R_o, and sensors) and the control loop (PI regulators, multipliers, and PWM comparators generating s_1 and s_2).
Because eHS runs the physical power circuit topology on the FPGA, here are the step-by-step instructions to prepare and import your model into OPAL-RT:
Step 1: Isolate the Power Stage in PSIM
Separate Power from Control: eHS is an FPGA electrical solver dedicated to simulating the power network (switches, diodes, passives, sources, and measurement probes). Control loops (PI controllers, filters, comparators) do not run directly inside the eHS FPGA netlist.
Configure Switch Gates:
Disconnect the control signals from the gates of Q_1 and Q_2.
Ensure the switches (Q_1, Q_2) and diodes are standard eHS-supported switch/diode components. Their gate signals will be supplied directly by eHS gate input ports (from hardware digital inputs or from the CPU/FPGA PWM generator).
Verify Sensors:
Keep your voltage sensor (V_{load}, V_{ac}) and current sensors (I_{ac}, I_{fb1}, I_{fb2}) in place. eHS will automatically expose these measurements as output signals.
Save the Schematic: Save the isolated power circuit as a .psimsch (or .sch) file in your project directory.
Step 2: Import into OPAL-RT (Schematic Editor / eHS Block)
Depending on whether you are using RT-LAB (Simulink) or HYPERSIM:
In RT-LAB (Simulink):
Add the OPAL-RT eHS Block (from the OPAL-RT / eFPGASIM library) into your SM_ master subsystem.
Double-click the eHS block and open the Schematic Editor / Configuration GUI.
Under the schematic source options, select PSIM and browse to select your saved .psimsch file.
The tool will parse the netlist, check component count against your eHS license/core capacity, and calculate the FPGA execution time step (typically 100\text{ ns} - 1,\mu\text{s}).
In HYPERSIM:
Add an eHS component from the HYPERSIM library into your grid schematic.
In the component properties, select PSIM format and link your .psimsch file.
Step 3: Map Gates and Measurements (HIL vs. RCP Workflow)
Decide where your control logic will execute:
Option A: Controller HIL (Testing a physical DSP / MCU board):
Gate inputs (Q_1, Q_2): Map to the target’s physical Digital Inputs (TSDIO / Fast Digital In) connected to your external controller’s PWM output pins.
Measurements (V_{load}, I_{fb1}, I_{fb2}): Map to the target’s physical Analog Outputs (DAC) connected to the DSP’s ADC sensing pins.
Option B: Pure Real-Time Simulation (Control running on Simulator CPU):
Implement the PI voltage/current control loops in Simulink / HYPERSIM running on the CPU (e.g., at 10,\mu\text{s} - 20,\mu\text{s}).
Feed the computed PWM/gate signals directly into the eHS software gate input ports.
Connect the eHS measurement outputs back to your CPU control feedback loop and scopes.
Step 4: Build and Execute
Click Build / Load in RT-LAB or HYPERSIM. The target will program the FPGA with your PFC netlist and run the real-time simulation.