# How can I increase the time step to 50us **URL:** \ **Category:** Q&A\ **Tags:** hypersim, discussion, energy, general\ **Created:** [September 9, 2026, 2:11am UTC](https://community.opal-rt.com/t/how-can-i-increase-the-time-step-to-50us/194 "2026-09-09T02:11:48Z")\ **Posts on this page:** 3\ **Page:** 1
**Author:** ![Vincent\_Jiang](https://yyz2.discourse-cdn.com/flex012/user_avatar/community.opal-rt.com/vincent_jiang/32/469_2.png) [@Vincent\_Jiang](https://community.opal-rt.com/u/Vincent_Jiang)\ **Post date:** [September 9, 2026, 2:11am UTC](https://community.opal-rt.com/t/how-can-i-increase-the-time-step-to-50us/194/1 "2026-09-09T02:11:48Z")
I am doing the simulaiton AC/DC and using PWM generator the switching frequency is 10kHz. If I set the time step at 50us, the simulated waveforms will be messy. So I need to decrease the time step to 1us, and the waveforms will be good. However, if I decrese the time step to 1us, I cannot use OP5707XG target to do simulation. How can I do? ![PWM generator.jpg](https://canada1.discourse-cdn.com/flex012/uploads/sps/original/1X/f4491b430d0c0211b23a3f2c79de63ceffd63d8c.jpeg) ---
**Author:** ![Parija](https://yyz2.discourse-cdn.com/flex012/user_avatar/community.opal-rt.com/parija/32/161_2.png) [@Parija](https://community.opal-rt.com/u/Parija)\ **Post date:** [September 16, 2026, 3:26pm UTC](https://community.opal-rt.com/t/how-can-i-increase-the-time-step-to-50us/194/2 "2026-09-16T15:26:30Z")
Hi, This is a classic challenge when simulating high-frequency power electronics in real time. At a 10\text{ kHz} switching frequency, the switching period (T\_{sw}) is 100,\mu\text{s}. Running at a 50,\mu\text{s} time step means the solver only samples the circuit 2 times per PWM cycle, which causes severe duty-cycle truncation, aliasing, and distorted (“messy”) waveforms. Dropping the CPU step to 1,\mu\text{s} fixes the resolution (100 points/cycle), but 1,\mu\text{s} exceeds the CPU computation budget per step on an OP5707XG target, leading to real-time overruns. CPU EMT solvers typically run stably between 10,\mu\text{s} and 50,\mu\text{s}. To solve this on the OP5707XG, here are the three recommended approaches depending on your simulation goals: 1. Best Approach: Use the OP5707XG Onboard FPGA with eHS (eFPGASIM / HYPERSIM) Since you are using an OP5707XG, you have access to a built-in Xilinx FPGA alongside your CPU cores. How it works: Move the AC/DC converter bridge and its passive filters (L/C) into the FPGA solver (OPAL-RT eHS / Schematic Editor). Execution rate: The FPGA solves the power electronics circuit at sub-microsecond steps (200\text{ ns} - 1,\mu\text{s}). Why it solves your issue: At 200\text{–}500\text{ ns}, you get 200 to 500 calculation points per PWM cycle, giving clean, distortion-free switching waveforms with zero CPU overruns. Co-simulation: Keep your grid, machine models, or slower network on the CPU running at 20\text{–}50,\mu\text{s}, and couple them using the Half-Line (stubline) or interface transformer. 1. CPU Alternative: Time-Stamped Interpolation (ARTEMiS / RT-Events) If you want to keep the simulation entirely on the CPU in SimPowerSystems / RT-LAB: How it works: Use the ARTEMiS Time-Stamped Bridge (TSB) or RT-Events (Time-Stamped PWM / TSM) blocks. Why it solves your issue: Standard solvers only update switch states at fixed time-step boundaries. Time-stamped blocks detect exact gate-signal switching events between time steps (sub-step interpolation) and mathematically compensate the equations. Result: You can run at T\_s = 20\text{–}50,\mu\text{s} on the CPU while maintaining accurate duty cycles and clean fundamental waveforms. 1. System-Level Alternative: Average-Value Model (AVM) If your objective is testing DC voltage regulation, grid interaction, or outer control loops rather than individual transistor switching harmonics: How it works: Replace the detailed switching IGBT/diode bridge with an Average-Value Converter Model (AVM). Result: The converter is represented by controlled continuous voltage/current sources modulated by duty cycle/modulation index. It runs accurately and efficiently on the CPU at T\_s = 50,\mu\text{s}. Recommended Next Steps For Controller HIL (cHIL) with real physical PWM inputs / fast switching: Configure the AC/DC bridge in eHS on the FPGA. For Software-in-the-Loop (SIL) / CPU-only real-time: Use ARTEMiS TSB (RT-LAB) or an Average-Value Model (HYPERSIM / RT-LAB). ---
**Author:** ![Vincent\_Jiang](https://yyz2.discourse-cdn.com/flex012/user_avatar/community.opal-rt.com/vincent_jiang/32/469_2.png) [@Vincent\_Jiang](https://community.opal-rt.com/u/Vincent_Jiang)\ **Post date:** [September 21, 2026, 4:31am UTC](https://community.opal-rt.com/t/how-can-i-increase-the-time-step-to-50us/194/3 "2026-09-21T04:31:18Z")
@Parija Thank you for your help. I will use eHs.