# Verbose mode decrease real-time performance **URL:** \ **Category:** Q&A\ **Tags:** hypersim, discussion, energy, general\ **Created:** [September 10, 2026, 7:15pm UTC](https://community.opal-rt.com/t/verbose-mode-decrease-real-time-performance/198 "2026-09-10T19:15:56Z")\ **Posts on this page:** 4\ **Page:** 1
**Author:** ![RAVITEJA](https://avatars.discourse-cdn.com/v4/letter/r/bc79bd/32.png) [@RAVITEJA](https://community.opal-rt.com/u/RAVITEJA)\ **Post date:** [September 10, 2026, 7:15pm UTC](https://community.opal-rt.com/t/verbose-mode-decrease-real-time-performance/198/1 "2026-09-10T19:15:56Z")
![image.png](https://canada1.discourse-cdn.com/flex012/uploads/sps/original/1X/84ba8e96ae192495934546916a82d6c2396c7046.png)Hi Team, Every time,I run the simulation ,I see a warning message saying “verbose mesage decreases real-time performance!” I tried cleaning the code directory. still i see this issue. is there a permanent solution for this ![1.png](https://canada1.discourse-cdn.com/flex012/uploads/sps/original/1X/df07930c308ad4a6b5489e61335febc3c392c1de.png) ---
**Author:** ![Parija](https://yyz2.discourse-cdn.com/flex012/user_avatar/community.opal-rt.com/parija/32/161_2.png) [@Parija](https://community.opal-rt.com/u/Parija)\ **Post date:** [September 16, 2026, 3:36pm UTC](https://community.opal-rt.com/t/verbose-mode-decrease-real-time-performance/198/2 "2026-09-16T15:36:44Z")
Hi, 1. Why Cleaning the Code Directory Does Not Resolve This Cleaning the code generation directory (or clearing slprj / temporary build folders) only deletes previously compiled binaries and cache files. However, Verbose Mode is a persistent configuration setting saved inside the model parameters (.slx/.mdl), the RT-LAB project configuration, or the communication driver masks. As soon as you rebuild or start the simulation, the model re-generates the real-time executable with verbose logging enabled. 1. Why This Warning Appears in Real-Time Simulation In hard real-time simulation on Linux/QNX targets, writing text messages (printf, std::cout, disp, or driver console logging) to stdout/stderr during the simulation step involves non-deterministic operating system I/O calls. These I/O operations stall the execution thread and can easily lead to timing overruns (missed time steps). The software generates this warning to alert you that active verbose/diagnostic logging is consuming target processor cycles. 1. Step-by-Step Permanent Solutions Please check the following four locations where verbose flags are typically enabled: Location A: Simulink Model Configuration Parameters (Code Generation) In MATLAB/Simulink, open your model and press Ctrl + E to open Model Configuration Parameters. Navigate to the Code Generation tab in the left pane. Under the General options, locate and uncheck “Verbose” (or set Verbose on build = off). Save the model (Ctrl + S) and rebuild in RT-LAB. Location B: RT-LAB Model Properties & Execution Settings In the RT-LAB Project Explorer, select your model or target node. Go to the Properties / Execution Options tab (or Simulation Controller settings). Look for “Verbose mode” or “Display verbose execution messages” and uncheck it. Set the Console / Log Verbosity Level to Normal or Errors/Warnings only instead of Verbose / Debug. Save the RT-LAB project (.opal). Location C: Communication Driver Blocks (I/O, Async, C37.118, CAN, SCPI, OpComm) Many communication blocks and protocol drivers in RT-LAB include a diagnostic verbose toggle: Check any communication / I/O blocks in your model (e.g., C37.118 Master/Slave, Async Controller, SCPI Driver, OpComm, OpCtrl). Double-click to open the block mask/configuration dialog. In the General or Advanced tab, uncheck “Enable verbose mode” or “Print diagnostic messages”. Save the model and recompile. Location D: Custom C S-Functions / MATLAB Function Blocks / UCM If your model contains custom C/C++ S-Functions, User Code Models (UCM), or MATLAB Function blocks: Ensure there are no active printf(…), std::cout, or disp(…) calls inside the main calculation loop (e.g., mdlOutputs or mdlUpdate). Comment these out or wrap them in preprocessor directives so they only execute offline during debugging: #ifdef DEBUG\_OFFLINE printf(“Debug value: %f\n”, var); #endif ---
**Author:** ![Loic007](https://avatars.discourse-cdn.com/v4/letter/l/7ab992/32.png) [@Loic007](https://community.opal-rt.com/u/Loic007)\ **Post date:** [September 17, 2026, 12:19am UTC](https://community.opal-rt.com/t/verbose-mode-decrease-real-time-performance/198/3 "2026-09-17T00:19:14Z")
Hi, Please try to uncheck “Enable Simulation Logging”. It should fix this message ![image.png](https://canada1.discourse-cdn.com/flex012/uploads/sps/original/1X/bac0f756d003266e98e937fde6e608cf44bf34c0.png) Usually, you enable this option to have more information displayed in the simout panel and help to debug initialisation or running a simulation. However, when the debug is completed, you should uncheck it. ---
**Author:** ![RAVITEJA](https://avatars.discourse-cdn.com/v4/letter/r/bc79bd/32.png) [@RAVITEJA](https://community.opal-rt.com/u/RAVITEJA)\ **Post date:** [September 17, 2026, 5:18am UTC](https://community.opal-rt.com/t/verbose-mode-decrease-real-time-performance/198/4 "2026-09-17T05:18:39Z")
Hi @Parija, I am currently working with HYPERSIM, so the RT-LAB-related suggestions may not be applicable to my setup. Nevertheless, I appreciate your prompt assistance and the information shared.