# Why halfline is required for FPGA and CPU cosimulation **URL:** \ **Category:** Q&A\ **Tags:** hypersim, discussion, energy, general\ **Created:** [September 9, 2026, 2:06am UTC](https://community.opal-rt.com/t/why-halfline-is-required-for-fpga-and-cpu-cosimulation/193 "2026-09-09T02:06:01Z")\ **Posts on this page:** 3\ **Page:** 1
**Author:** ![Vincent\_Jiang](https://yyz2.discourse-cdn.com/flex012/user_avatar/community.opal-rt.com/vincent_jiang/32/469_2.png) [@Vincent\_Jiang](https://community.opal-rt.com/u/Vincent_Jiang)\ **Post date:** [September 9, 2026, 2:06am UTC](https://community.opal-rt.com/t/why-halfline-is-required-for-fpga-and-cpu-cosimulation/193/1 "2026-09-09T02:06:01Z")
I am doing FPGA and CPU co-simulation in Hypersim. I do not know why halfline is required for FPGA and CPU co-simulation? ![Halfline model.jpg](https://canada1.discourse-cdn.com/flex012/uploads/sps/original/1X/4077c4b5915c987e1c898d9b44977ae1bd706576.jpeg) ---
**Author:** ![Parija](https://yyz2.discourse-cdn.com/flex012/user_avatar/community.opal-rt.com/parija/32/161_2.png) [@Parija](https://community.opal-rt.com/u/Parija)\ **Post date:** [September 16, 2026, 2:58pm UTC](https://community.opal-rt.com/t/why-halfline-is-required-for-fpga-and-cpu-cosimulation/193/2 "2026-09-16T14:58:59Z")
Hi, When setting up a co-simulation between CPU (HYPERSIM) and FPGA (eHS / Schematic Editor), you will encounter the Half-Line (also known as a stubline or decoupling line) block at the boundary between the two solvers. Here is a breakdown of why the half-line is essential, the underlying mathematics, and best practices for configuring it in your models. 1. The Core Challenge: Breaking the Nodal Matrix Dependency In real-time Electromagnetic Transient (EMT) simulation, if two electrical subsystems are directly connected at an electrical bus, their voltages and currents are coupled instantaneously. This requires solving a single, global nodal admittance matrix: [G] \cdot [V(t)] = [I(t)] The Problem: The CPU and FPGA are two physically distinct computation targets. They cannot instantaneously solve a shared system of equations at the same exact microsecond without stalling each other. The Solution: The Half-Line model mathematically decouples the global system of equations into two independent subsystems (one solved on the CPU and one on the FPGA). 1. How the Half-Line Works (Bergeron / Traveling Wave Principle) The Half-Line is based on the Bergeron method (traveling wave line model): In a physical line or stubline, an electromagnetic wave takes a finite amount of time (\tau) to travel from one end to the other. Because of this propagation delay, the voltage and current at one end of the line at time t depend only on the local conditions at time t and the past history terms from the other end at (t - \tau). By placing half of the decoupling line in the CPU model (HYPERSIM) and the matching half in the FPGA model (eHS / Schematic Editor), each solver uses past values received via communication buffers without needing the other solver’s instantaneous state. 2. Bridging the Multirate & Latency Gap FPGA and CPU solvers operate at vastly different rates: FPGA (eHS): Typically runs at sub-microsecond steps (e.g., 100\text{ ns} - 1,\mu\text{s}) to capture high-frequency PWM and fast switching transients. CPU (HYPERSIM): Typically runs at larger timesteps (e.g., 10 - 50,\mu\text{s}) to simulate large power networks and machines efficiently. Hardware Latency: Transferring data between the CPU and FPGA introduces a communication delay (typically 2 to 3 CPU timesteps). The half-line’s Round-Trip Latency parameter absorbs this communication delay into the simulation equations as a physical propagation delay, ensuring numerical stability across multirate boundaries. 1. Physical Circuit Representation & Best Practices Parameter / Choice Best Practice / Physical Meaning Inductive vs. Capacitive The half-line can be configured as an inductance (series element) or capacitance (shunt element). Where to Place It The ideal location is across existing physical impedances, such as the leakage inductance of an interface transformer (e.g., converter step-up transformer) or a filter inductor/choke. Parameter Matching Ensure the Inductance/Capacitance and Decoupling Latency values set in the Schematic Editor match the sister block in HYPERSIM. Minimizing Numerical Distortion Place the decoupling boundary where system dynamics are relatively slower (e.g., grid side of a transformer rather than inside a fast resonant tank), or choose a sufficiently large inductance to keep decoupling errors negligible. Summary Without the half-line, real-time FPGA + CPU co-simulation would require solving simultaneous algebraic equations across different hardware targets, which is impossible in real time. The half-line introduces a physically accurate propagation delay that decouples the mathematical matrices, allowing eHS on FPGA to simulate fast switching while HYPERSIM on CPU solves the wide-area power system in parallel. ---
**Author:** ![Vincent\_Jiang](https://yyz2.discourse-cdn.com/flex012/user_avatar/community.opal-rt.com/vincent_jiang/32/469_2.png) [@Vincent\_Jiang](https://community.opal-rt.com/u/Vincent_Jiang)\ **Post date:** [September 21, 2026, 4:58am UTC](https://community.opal-rt.com/t/why-halfline-is-required-for-fpga-and-cpu-cosimulation/193/3 "2026-09-21T04:58:53Z")
@Parija Thank you for your explanation.