Step time too small when connected to OP5707XG

I ran the microgrid simulation in hypersim and connected it to OP5707XG.
It showed the following message.
I do not know the reason.

When I changed the time step to 52us ,and I ran the simulation in OP5707XG.
It was always in the mode as shown below.

Hello @Vincent_Jiang

Thank you for sharing the screenshots. Seeing the exact error messages helps clarify what is happening at each stage:

  1. Understanding the First Error (Task BUS15: execution time 47.4773 µs is too large)
    During the task mapping phase, HYPERSIM evaluates the estimated calculation time for each sub-network task.
    Task BUS15 alone requires 47.48,\mu\text{s} of computational time on the core.
    Adding the system communication and safety margin overhead (around 4,\mu\text{s}), HYPERSIM flags that the model strictly requires a time step > 51.48,\mu\text{s}.

  2. Why it Hangs at “Generating and building the design simulation code / Network changes treated”
    When you increased the time step to 52,\mu\text{s}, two issues occur:
    Margin is Too Tight:
    52,\mu\text{s} is only \approx 0.5,\mu\text{s} above the minimum limit (51.48,\mu\text{s}). In real-time execution, this almost inevitably leads to instant overruns or synchronization deadlocks on the target cores.
    Stuck Build/Compilation Process on the Target:
    When changing the time step, HYPERSIM must regenerate the C code, recompile it, and transfer the new binaries to the OP5707XG target. If the previous simulation process did not cleanly terminate or is holding a lock on the target:
    The compiler process or SSH file transfer hangs at the code generation/build stage (“Network changes treated”).

Recommended Solutions
Step A: Reset and Clean the Build
In HYPERSIM, click Stop (if active) and do a clean rebuild: Simulation > Clean Code / Rebuild.
Restart the HYPERSIM software, or reboot the OP5707XG target via the target manager to clear any hanging simulation processes from memory.

Step B: Increase the Time Step Margin
Try setting the time step to 60,\mu\text{s} or 70,\mu\text{s} first.
This provides sufficient headroom for Task BUS15, the solver overhead, and I/O exchanges.

Step C: Partition and Optimize Task BUS15 (To keep a lower time step)
If your microgrid requires a faster time step (e.g., 30\text{–}50,\mu\text{s}):
Split Task BUS15: Identify the network around BUS15 in your schematic. If this sub-network contains too many nodes or detailed switching components, insert a Decoupling Line (Bergeron traveling-wave line or transformer decoupling with propagation time \tau \ge \Delta t).
Multicore Allocation: Once decoupled, assign the split sub-networks to separate CPU cores (e.g., Task 1 on Core 1, Task 2 on Core 2) in the Task Manager / Core Assignment settings.

@Parija Thank you for your help. I have two cores in my OP5707XG. Will it become faster by using more cores?
On the ohter hand, do you mind if I send the file to you and help me do the “traveling-wave line or transformer decoupling with propagation time .”
Thank you.