Building scalable HIL test benches: OPAL-RT + NI hardware integration for electrified propulsion

Sharing a general framework rather than a specific setup — this comes up often when scaling HIL benches for electrified propulsion (eVTOL, EV/HEV) and I think it’s worth discussing openly.

When the goal is a scalable, DUT-agnostic test bench (not just a one-off validation setup), a few structural blocks tend to show up regardless of the specific application:

Signal generation and acquisition decoupled from the real-time core, so instrumentation can scale independently of simulation complexity
Driver/interface layer between the real-time simulator and the physical DUT — this is usually where OPAL-RT + NI hardware integration does the heavy lifting, especially when VeriStand is used to unify data acquisition and test sequencing. On the compute side, this is also where FPGA headroom matters: platforms like OPAL-RT’s Versal-based (OP4810 or OP4815) systems can integrate directly with NI PXI hardware while still having enough onboard compute to simulate multiple PMSM motors in parallel — relevant for distributed propulsion scenarios where you need to test multi-motor redundancy or single-motor failure cases without re-architecting the bench for each configuration
Load emulation sized and architected early, not bolted on later — this is often the piece that limits scalability if underestimated
Independent safety/emergency layer, isolated from the main control path, monitoring all interfaces rather than just the DUT
Power supply segregation (LV control/signal path vs. HV power path) planned from the start, not as an afterthought

In practice, the OPAL-RT Integration experstive (NI and OPAL-RT hardware plus VeriStand) — tends to be where the “last mile” integration challenge lives: connecting a validated real-time model to physical instrumentation and test sequencing without losing determinism or scalability.

Curious how others are structuring this, especially when the DUT is a customer-supplied subsystem rather than something the test bench was originally designed around — that’s usually where the architecture gets tested the most.

Wow @jefcintra super impressed tell us more I do not see Fault Injection Unit in your design but Break-out box, could you clarify, when we use Break-Out Box vs Faut Insertion Unit vs both ?