I want to generate a 100kHz pulse train that will fed to MOSFET. As i am new to this will anyone suggest me for this
Method 1: RT-LAB (Hardware Digital Output via OPAL-RT Board Driver)
In RT-LAB, PWM signals are typically generated on the target FPGA using the OPAL-RT Board driver.
Configuration Steps:
Configure the Hardware Bitstream:
In your RT-LAB project, open the OPAL-RT Board Driver configuration panel.
Parse your target bitstream configuration file (.conf or .bin).
Set Channel Mode to PWM:
Navigate to the Digital Output (DO) module and select the desired channel group (grouped in blocks of 8).
Set Digital Type to Pulse width modulated (PWM).
Check Enable. This exposes connection points for Frequency and Duty Cycle for each channel in the RT-LAB configuration tree.
Connect Signals in Simulink:
In your Simulink model (sm_ subsystem), add OpOutput blocks connected to the OPAL-RT driver ports.
Feed a constant or variable signal of 100000 (Hz) into the Frequency port.
Feed your desired Duty Cycle (e.g., 0.5 for 50%) into the Duty Cycle port.
Set Switching Parameters:
Wave Mode: Choose Symmetric (center-aligned) or Asymmetric (edge-aligned).
Polarity: Active High (0\text{ V} \rightarrow 5\text{ V}).
Dead Time: If driving complementary MOSFETs in a half-bridge/full-bridge topology, specify dead time (e.g., 100\text{ ns} - 500\text{ ns}) to prevent shoot-through currents.
Reference:
PWM Outputs
Method 2: HYPERSIM (Hardware Output & Software Simulation)
HYPERSIM supports both hardware signal output to physical pins and internal model-based PWM generation for hardware-in-the-loop (HIL) or power system simulation.
Option A: Physical Hardware Output (OPAL-RT Board Driver)
Open HYPERSIM Schematic Editor and access the I/O & Hardware Configuration.
Parse your target bitstream and navigate to the Digital Output channels.
Change Digital Type to Pulse width modulated (PWM) and enable the group.
Map the Frequency (100,000\text{ Hz}) and Duty Cycle signals from your control block diagram in the HYPERSIM schematic directly to the hardware connection points.
Option B: Model-Based PWM Generation (Internal Simulation)
If you are simulating the MOSFET within the HYPERSIM real-time model rather than feeding a physical external device:
Drag the PWM Generation Block and Carrier Signal Generation Block from the library into your schematic.
Set the carrier frequency to 100000 Hz.
Critical Setting (Interpolation Mode): Because a 100\text{ kHz} signal has a period of 10\ \mu\text{s}, a standard simulation timestep (e.g., 10\ \mu\text{s} or 20\ \mu\text{s}) can alias or miss switching events. Set the comparison mode to TOM (Time On Mean) or ATOM (Advanced TOM). These modes interpolate turn-on and turn-off events between timesteps to maintain sub-microsecond pulse accuracy.
References:
PWM Out |
PWM Generation Block
Crucial Hardware Interface Note (Gate Driver IC)
The Digital Output (DO) pins on OPAL-RT simulator carrier boards (e.g., OP4510, OP5600, OP5700) typically output 5V TTL or 3.3V LVTTL logic levels with low drive current capabilities (~20 mA).